1. Field of the Invention
The present invention relates to an apparatus, a method, and a computer program product for processing information by controlling hardware arithmetic processing according to asynchronous and synchronous mode that can reduce a load on a processor unit.
2. Description of the Related Art
Recently, a broadband network has been popularized in government agencies, corporations, education institutions, and homes, and there is growing interest in network security for preventing information leakage and data falsification. For communication data transferred via a communication line, tapping and falsification can be prevented by using cryptographic technology and message authentication (digest authentication, hash authentication, keyed-hashing for message authentication code (HMAC) authentication), thereby enabling to improve the security.
Representative communication protocols for improving the security of the communication data include IPsec and Transport Layer Security (TLS) specified by the Internet Engineering Task Force (IETF) and the Wired Equivalent Privacy (WEP) specified by the Institute of Electrical and Electronics Engineers, Inc. (IEEE). Further, the cryptographic technology is used for preventing illegal copying of literary works and preventing illegal outflow of personal information, business confidential information, and confidential information involved with national defense.
Recently, further, high-definition and high-quality digital broadcasting and digital music distribution are popularized. For various digital data such as digital speech data, image data, and video data, reduction of data amount to be stored and reduction of data transfer capacity per unit time of the communication line can be realized by using a data compression technique. Particularly, because data amount is increasing due to high definition of the image data and the video data, the compression technique becomes essential.
Representative compression techniques of digital image data and digital video data include Joint Photographic Experts Group (JPEG) and Moving Picture Experts Group (MPEG)(registered trademark). Representative compression techniques of digital speech data include Advanced Audio Coding (AAC)(registered trademark), MPEG-1 for Audio Layer-3 (MP3), and Adaptive Transform Acoustic Coding (ATRAC)(registered trademark).
Arithmetic processing such as encryption and data compression processing is realized in many cases by executing a sequence of instruction (program) on a general-purpose processing unit (PU) equipped in a general-purpose computer. According to this method, however, the data amount to be processed per unit time increases with an increase in the data amount and communication data rate, to increase a load on the arithmetic processing performed on the general-purpose PU.
With respect to such a problem, the arithmetic processing load on the PU can be reduced by installing an apparatus that performs specific arithmetic processing (hereinafter, “HW arithmetic unit”) in addition to the general-purpose PU in the general-purpose computer. Thus, execution of the arithmetic processing by the HW arithmetic unit is frequently referred to as hardware offloading or hardware arithmetic processing.
Regarding the hardware arithmetic processing, JP-A 2006-7638 (KOKAI) and JP-A 2004-180253 (KOKAI) disclose a technique for changing over software arithmetic processing and hardware arithmetic processing, to execute the arithmetic processing such as the encryption processing and the data compression processing by either the HW arithmetic unit or the PU, whichever is faster.
On the other hand, the method of controlling the HW arithmetic unit from the program operating on the general-purpose PU can be divided into the synchronous mode and the asynchronous mode. In the synchronous mode, processing for waiting for termination of the processing by the HW arithmetic unit (hereinafter, “HW operation-termination waiting processing”) is performed, when the arithmetic processing is requested from the program operating on the general-purpose PU to the HW arithmetic unit. The synchronous mode is mainly adopted by a program for performing the arithmetic processing by the HW arithmetic unit.
In the asynchronous mode, software processing is divided into processing up to the hardware arithmetic processing (hereinafter, “preprocessing”) and processing after the hardware arithmetic processing (hereinafter, “postprocessing”) and executed, without waiting for the termination of the processing by the HW arithmetic unit. In the asynchronous mode, because the processing is divided before and after the hardware arithmetic processing and executed, processing for passing data held by the preprocessing (example: parameters relating to the hardware arithmetic processing and data subjected to the hardware arithmetic processing) on to the postprocessing (hereinafter, “asynchronous processing”) is required. As an example of the asynchronous processing, there is an operation for passing all or a part of the data held by the preprocessing on to the postprocessing, or an operation for passing a memory address of all or a part of the data held by the preprocessing on to the postprocessing.
In A. D. Keromytis et al., “The Design of the OpenBSD Cryptographic Framework”, 2003 USENIX Annual Technical Conference, USENIX Association, 2003, a program for controlling the HW arithmetic unit that performs encryption and decryption according to the asynchronous mode is described. Currently, however, examples adopting the asynchronous mode are fewer than examples adopting the synchronous mode.
According to the asynchronous mode, termination of the processing by the HW arithmetic unit need not be waited for as in the synchronous mode. Therefore, the load on the PU during the arithmetic processing by the HW arithmetic unit can be reduced as compared to that in the synchronous mode. Accordingly, when the asynchronous mode can be adopted, generally, the HW arithmetic unit is controlled only according to the asynchronous mode.
Depending on the type of the arithmetic processing, however, control of the HW arithmetic unit according to the asynchronous mode can be unsuitable. For example, when the load on the PU in the asynchronous processing according to the asynchronous mode is higher than the load on the PU in the HW operation termination waiting processing according to the synchronous mode, the load on the PU can be reduced further by controlling the HW arithmetic unit according to the synchronous mode. That is, there is a problem that even in an apparatus designed to control the HW arithmetic unit according to the asynchronous mode to reduce the load on the PU, the load on the PU can be increased on the contrary.
Further, in the case of the asynchronous mode, processing delay higher than that in the synchronous mode occurs by the time required for performing the asynchronous processing. In the asynchronous mode, because the processing is divided before and after the hardware arithmetic processing, time fluctuation until the postprocessing is executed on the PU is larger than that in the synchronous mode. Therefore, in the asynchronous mode, there is a problem that an increase of the processing delay and fluctuation (jitter) of the processing delay occur, and therefore the asynchronous mode is not suitable for the processing requiring real-time performance.